US Patent Issued to Micron Technology on May 26 for "Method used in forming memory circuitry comprising stairs in a stair-step region using first and second layers of imageable resist" (American, Italian Inventors)

ALEXANDRIA, Va., May 26 -- United States Patent no. 12,640,202, issued on May 26, was assigned to Micron Technology Inc. (Boise, Idaho). "Method used in forming memory circuitry comprising stairs in ... Read More

US Patent Issued to Micron Technology on May 26 for "Adaptive wordline start voltage using wordline sampling" (Singaporean Inventors)

ALEXANDRIA, Va., May 26 -- United States Patent no. 12,640,203, issued on May 26, was assigned to Micron Technology Inc. (Boise, Idaho). "Adaptive wordline start voltage using wordline sampling" was ... Read More

US Patent Issued to SK hynix on May 26 for "Memory device" (South Korean Inventors)

ALEXANDRIA, Va., May 26 -- United States Patent no. 12,640,204, issued on May 26, was assigned to SK hynix Inc. (Icheon-si, South Korea). "Memory device" was invented by Chan Hui Jeong (Icheon-si, So... Read More

US Patent Issued to Yangtze Memory Technologies on May 26 for "Memory and multi-initialization operation operating method thereof, memory system and readable storage medium" (Chinese Inventor)

ALEXANDRIA, Va., May 26 -- United States Patent no. 12,640,205, issued on May 26, was assigned to Yangtze Memory Technologies Co. Ltd. (Wuhan, China). "Memory and multi-initialization operation opera... Read More

US Patent Issued to Sandisk Technologies on May 26 for "Post-program erase in 3D NAND" (Chinese Inventors)

ALEXANDRIA, Va., May 26 -- United States Patent no. 12,640,206, issued on May 26, was assigned to Sandisk Technologies Inc. (Milpitas, Calif.). "Post-program erase in 3D NAND" was invented by Ming Wa... Read More

US Patent Issued to Micron Technology on May 26 for "Selectively erasing one of multiple erase blocks coupled to a same string by creating a pseudo PN junction" (Singaporean, American, Japanese, Italian Inventors)

ALEXANDRIA, Va., May 26 -- United States Patent no. 12,640,207, issued on May 26, was assigned to Micron Technology Inc. (Boise, Idaho). "Selectively erasing one of multiple erase blocks coupled to a... Read More

US Patent Issued to STMicroelectronics International on May 26 for "Method for corrupting data stored in a memory, and corresponding integrated circuit" (French Inventor)

ALEXANDRIA, Va., May 26 -- United States Patent no. 12,640,208, issued on May 26, was assigned to STMicroelectronics International N.V. (Geneva). "Method for corrupting data stored in a memory, and c... Read More

US Patent Issued to INTEL NDTM US on May 26 for "Modulation of source voltage in NAND-flash array read" (California Inventor)

ALEXANDRIA, Va., May 26 -- United States Patent no. 12,640,209, issued on May 26, was assigned to INTEL NDTM US LLC (Santa Clara, Calif.). "Modulation of source voltage in NAND-flash array read" was ... Read More

US Patent Issued to SAMSUNG ELECTRONICS on May 26 for "Serial interface receiver and an offset calibration method thereof" (South Korean Inventors)

ALEXANDRIA, Va., May 26 -- United States Patent no. 12,640,210, issued on May 26, was assigned to SAMSUNG ELECTRONICS Co. LTD. (Suwon-si, South Korea). "Serial interface receiver and an offset calibr... Read More

US Patent Issued to Micron Technology on May 26 for "Read disturb detection in a memory system" (Idaho, California Inventors)

ALEXANDRIA, Va., May 26 -- United States Patent no. 12,640,211, issued on May 26, was assigned to Micron Technology Inc. (Bosie, Idaho). "Read disturb detection in a memory system" was invented by De... Read More

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