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US Patent Issued to International Business Machines on Sept. 8 for "Dual damascene fully-aligned via interconnects with dual etch layers" (American, Chinese Inventors)

ALEXANDRIA, Va., Sept. 8 -- United States Patent no. 12,733,472, issued on Sept. 8, was assigned to International Business Machines Corp. (Armonk, N.Y.). "Dual damascene fully-aligned via interconnec... Read More


US Patent Issued to TAIWAN SEMICONDUCTOR MANUFACTURING on Sept. 8 for "Selective deposition of barrier layer" (Taiwanese Inventors)

ALEXANDRIA, Va., Sept. 8 -- United States Patent no. 12,733,473, issued on Sept. 8, was assigned to TAIWAN SEMICONDUCTOR MANUFACTURING Co. LTD. (Hsinchu, Taiwan). "Selective deposition of barrier lay... Read More


US Patent Issued to MACOM TECHNOLOGY SOLUTIONS HOLDINGS on Sept. 8 for "Unibody lateral via" (Massachusetts, California, New Hampshire Inventors)

ALEXANDRIA, Va., Sept. 8 -- United States Patent no. 12,733,474, issued on Sept. 8, was assigned to MACOM TECHNOLOGY SOLUTIONS HOLDINGS INC. (Lowell, Mass.). "Unibody lateral via" was invented by And... Read More


US Patent Issued to SAMSUNG ELECTRONICS on Sept. 8 for "Semiconductor package with dummy pads" (South Korean Inventors)

ALEXANDRIA, Va., Sept. 8 -- United States Patent no. 12,733,475, issued on Sept. 8, was assigned to SAMSUNG ELECTRONICS Co. LTD. (Suwon-si, South Korea). "Semiconductor package with dummy pads" was i... Read More


US Patent Issued to SAMSUNG ELECTRONICS on Sept. 8 for "Semiconductor device and method of fabricating the same" (South Korean Inventors)

ALEXANDRIA, Va., Sept. 8 -- United States Patent no. 12,733,476, issued on Sept. 8, was assigned to SAMSUNG ELECTRONICS Co. Ltd. (Gyeonggi-do, South Korea). "Semiconductor device and method of fabric... Read More


US Patent Issued to Intel on Sept. 8 for "Damascene interconnect structures with low resistance vias for integrated circuits" (Oregon Inventors)

ALEXANDRIA, Va., Sept. 8 -- United States Patent no. 12,733,477, issued on Sept. 8, was assigned to Intel Corp. (Santa Clara, Calif.). "Damascene interconnect structures with low resistance vias for ... Read More


US Patent Issued to Intel on Sept. 8 for "Selective bottomless graphene lined interconnects" (Oregon Inventors)

ALEXANDRIA, Va., Sept. 8 -- United States Patent no. 12,733,478, issued on Sept. 8, was assigned to Intel Corp. (Santa Clara, Calif.). "Selective bottomless graphene lined interconnects" was invented... Read More


US Patent Issued to Intel on Sept. 8 for "Integrated circuit (IC) device with multilayer metal line" (Oregon, New Mexico Inventors)

ALEXANDRIA, Va., Sept. 8 -- United States Patent no. 12,733,479, issued on Sept. 8, was assigned to Intel Corp. (Santa Clara, Calif.). "Integrated circuit (IC) device with multilayer metal line" was ... Read More


US Patent Issued to COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES on Sept. 8 for "Device for detecting an electromagnetic radiation including a thermal detector over a readout substrate an active electronic element of which is located the closest to the thermal detector" (French Inventors)

ALEXANDRIA, Va., Sept. 8 -- United States Patent no. 12,733,480, issued on Sept. 8, was assigned to COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES (Paris). "Device for detecting an el... Read More


US Patent Issued to TAIWAN SEMICONDUCTOR MANUFACTURING on Sept. 8 for "Device having different first metallization layer and first buried metallization layer architectures and method of manufacturing same" (Taiwanese Inventors)

ALEXANDRIA, Va., Sept. 8 -- United States Patent no. 12,733,481, issued on Sept. 8, was assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD. (Hsinchu, Taiwan). "Device having different first m... Read More