US Patent Issued to NANYA TECHNOLOGY on Nov. 3 for "Semiconductor device structure with liner layer having tapered sidewall and method for preparing the same" (Taiwanese Inventor)

Posted On: 2026-11-03

ALEXANDRIA, Va., Nov. 3 -- United States Patent no. 12,787,734, issued on Nov. 3, was assigned to NANYA TECHNOLOGY Corp. (New Taipei City, Taiwan). "Semiconductor device structure with liner layer ha... Read More

US Patent Issued to NANYA TECHNOLOGY on Nov. 3 for "Semiconductor device with porous layer and method for fabricating the same" (Taiwanese Inventor)

Posted On: 2026-11-03

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ALEXANDRIA, Va., Nov. 3 -- United States Patent no. 12,787,735, issued on Nov. 3, was assigned to NANYA TECHNOLOGY Corp. (New Taipei City, Taiwan). "Semiconductor device with porous layer and method ... Read More

US Patent Issued to NANYA TECHNOLOGY on Nov. 3 for "Semiconductor device with porous layer and method for fabricating the same" (Taiwanese Inventor)

Posted On: 2026-11-03

Government News US Fed News Patentwipo

ALEXANDRIA, Va., Nov. 3 -- United States Patent no. 12,787,736, issued on Nov. 3, was assigned to NANYA TECHNOLOGY Corp. (New Taipei City, Taiwan). "Semiconductor device with porous layer and method ... Read More

US Patent Issued to NANYA TECHNOLOGY on Nov. 3 for "Method of manufacturing semiconductor structure" (Taiwanese Inventor)

Posted On: 2026-11-03

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ALEXANDRIA, Va., Nov. 3 -- United States Patent no. 12,787,737, issued on Nov. 3, was assigned to NANYA TECHNOLOGY Corp. (New Taipei City, Taiwan). "Method of manufacturing semiconductor structure" w... Read More

US Patent Issued to SAMSUNG ELECTRONICS on Nov. 3 for "Semiconductor devices and data storage systems including the same" (South Korean Inventors)

Posted On: 2026-11-03

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ALEXANDRIA, Va., Nov. 3 -- United States Patent no. 12,787,738, issued on Nov. 3, was assigned to SAMSUNG ELECTRONICS Co. Ltd. (Gyeonggi-do, South Korea). "Semiconductor devices and data storage syst... Read More

US Patent Issued to International Business Machines on Nov. 3 for "Super via within backside level" (New York Inventors)

Posted On: 2026-11-03

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ALEXANDRIA, Va., Nov. 3 -- United States Patent no. 12,787,739, issued on Nov. 3, was assigned to International Business Machines Corp. (Armonk, N.Y.). "Super via within backside level" was invented ... Read More

US Patent Issued to SAMSUNG ELECTRONICS on Nov. 3 for "Integrated circuit device including a power rail" (South Korean Inventors)

Posted On: 2026-11-03

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ALEXANDRIA, Va., Nov. 3 -- United States Patent no. 12,787,740, issued on Nov. 3, was assigned to SAMSUNG ELECTRONICS Co. LTD. (Suwon-si, South Korea). "Integrated circuit device including a power ra... Read More

US Patent Issued to GLOBALFOUNDRIES U.S. on Nov. 3 for "Structure with cavity around through semiconductor via" (New York Inventors)

Posted On: 2026-11-03

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ALEXANDRIA, Va., Nov. 3 -- United States Patent no. 12,787,741, issued on Nov. 3, was assigned to GLOBALFOUNDRIES U.S. INC. (Malta, N.Y.). "Structure with cavity around through semiconductor via" was... Read More

US Patent Issued to SAMSUNG ELECTRONICS on Nov. 3 for "Integrated circuit devices including stacked transistors and methods of forming the same" (New York, Virginia Inventors)

Posted On: 2026-11-03

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ALEXANDRIA, Va., Nov. 3 -- United States Patent no. 12,787,742, issued on Nov. 3, was assigned to SAMSUNG ELECTRONICS Co. Ltd. (South Korea). "Integrated circuit devices including stacked transistors... Read More

US Patent Issued to Intel on Nov. 3 for "Methods, systems, apparatus, and articles of manufacture to produce integrated circuit packages with grounding members" (Arizona, Oregon Inventors)

Posted On: 2026-11-03

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ALEXANDRIA, Va., Nov. 3 -- United States Patent no. 12,787,743, issued on Nov. 3, was assigned to Intel Corp. (Santa Clara, Calif.). "Methods, systems, apparatus, and articles of manufacture to produ... Read More

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US Patent Issued to NANYA TECHNOLOGY on Nov. 3 for "Semiconductor device structure with liner layer having tapered sidewall and method for preparing the same" (Taiwanese Inventor)

US Patent Issued to NANYA TECHNOLOGY on Nov. 3 for "Semiconductor device with porous layer and method for fabricating the same" (Taiwanese Inventor)

US Patent Issued to NANYA TECHNOLOGY on Nov. 3 for "Semiconductor device with porous layer and method for fabricating the same" (Taiwanese Inventor)

US Patent Issued to NANYA TECHNOLOGY on Nov. 3 for "Method of manufacturing semiconductor structure" (Taiwanese Inventor)

US Patent Issued to SAMSUNG ELECTRONICS on Nov. 3 for "Semiconductor devices and data storage systems including the same" (South Korean Inventors)

US Patent Issued to International Business Machines on Nov. 3 for "Super via within backside level" (New York Inventors)

US Patent Issued to SAMSUNG ELECTRONICS on Nov. 3 for "Integrated circuit device including a power rail" (South Korean Inventors)

US Patent Issued to GLOBALFOUNDRIES U.S. on Nov. 3 for "Structure with cavity around through semiconductor via" (New York Inventors)

US Patent Issued to SAMSUNG ELECTRONICS on Nov. 3 for "Integrated circuit devices including stacked transistors and methods of forming the same" (New York, Virginia Inventors)

US Patent Issued to Intel on Nov. 3 for "Methods, systems, apparatus, and articles of manufacture to produce integrated circuit packages with grounding members" (Arizona, Oregon Inventors)