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US Patent Issued to ASM IP Holding on April 14 for "Method and system for mitigating underlayer damage during formation of patterned structures" (Japanese Inventors)

ALEXANDRIA, Va., April 15 -- United States Patent no. 12,604,684, issued on April 14, was assigned to ASM IP Holding B.V. (Almere, Netherlands). "Method and system for mitigating underlayer damage du... Read More


US Patent Issued to Tokyo Electron on April 14 for "Methods for controlling spin-on self-assembled monolayer (SAM) selectivity" (New York Inventors)

ALEXANDRIA, Va., April 15 -- United States Patent no. 12,604,685, issued on April 14, was assigned to Tokyo Electron Ltd. (Tokyo). "Methods for controlling spin-on self-assembled monolayer (SAM) sele... Read More


US Patent Issued to Tokyo Electron on April 14 for "Methods for controlling spin-on self-assembled monolayer (SAM) selectivity" (New York Inventors)

ALEXANDRIA, Va., April 15 -- United States Patent no. 12,604,685, issued on April 14, was assigned to Tokyo Electron Ltd. (Tokyo). "Methods for controlling spin-on self-assembled monolayer (SAM) sele... Read More


US Patent Issued to SAMSUNG ELECTRONICS on April 14 for "Semiconductor chip and semiconductor package including the same" (South Korean Inventors)

ALEXANDRIA, Va., April 15 -- United States Patent no. 12,604,686, issued on April 14, was assigned to SAMSUNG ELECTRONICS Co. LTD. (Suwon-si, South Korea). "Semiconductor chip and semiconductor packa... Read More


US Patent Issued to SAMSUNG ELECTRONICS on April 14 for "Semiconductor chip and semiconductor package including the same" (South Korean Inventors)

ALEXANDRIA, Va., April 15 -- United States Patent no. 12,604,686, issued on April 14, was assigned to SAMSUNG ELECTRONICS Co. LTD. (Suwon-si, South Korea). "Semiconductor chip and semiconductor packa... Read More


US Patent Issued to Destination 2D on April 14 for "Large-area/wafer-scale CMOS-compatible 2D-material intercalation doping tools, processes, and methods, including intercalation doping of synthesized and patterned graphene" (California, Oregon Inventors)

ALEXANDRIA, Va., April 15 -- United States Patent no. 12,604,687, issued on April 14, was assigned to Destination 2D Inc. (San Jose, Calif.). "Large-area/wafer-scale CMOS-compatible 2D-material inter... Read More


US Patent Issued to Destination 2D on April 14 for "Large-area/wafer-scale CMOS-compatible 2D-material intercalation doping tools, processes, and methods, including intercalation doping of synthesized and patterned graphene" (California, Oregon Inventors)

ALEXANDRIA, Va., April 15 -- United States Patent no. 12,604,687, issued on April 14, was assigned to Destination 2D Inc. (San Jose, Calif.). "Large-area/wafer-scale CMOS-compatible 2D-material inter... Read More


US Patent Issued to SHIN-ETSU HANDOTAI on April 14 for "Method for manufacturing SOI wafer" (Japanese Inventors)

ALEXANDRIA, Va., April 15 -- United States Patent no. 12,604,688, issued on April 14, was assigned to SHIN-ETSU HANDOTAI Co. LTD. (Tokyo). "Method for manufacturing SOI wafer" was invented by Hiroji ... Read More


US Patent Issued to SHIN-ETSU HANDOTAI on April 14 for "Method for manufacturing SOI wafer" (Japanese Inventors)

ALEXANDRIA, Va., April 15 -- United States Patent no. 12,604,688, issued on April 14, was assigned to SHIN-ETSU HANDOTAI Co. LTD. (Tokyo). "Method for manufacturing SOI wafer" was invented by Hiroji ... Read More


US Patent Issued to NANYA TECHNOLOGY on April 14 for "Bracing structure, semiconductor device with the same, and method for fabricating the same" (Taiwanese Inventor)

ALEXANDRIA, Va., April 15 -- United States Patent no. 12,604,689, issued on April 14, was assigned to NANYA TECHNOLOGY Corp. (New Taipei City, Taiwan). "Bracing structure, semiconductor device with t... Read More