India, April 16 -- Ahead of TSMC's earnings call, the spotlight is once again on its advanced packaging roadmap-and CoWoS is no longer the only story. According to Commercial Times, TSMC's CoPoS (Chip-on-Panel-on-Substrate) pilot line has already begun tool deliveries to R&D teams in February, with the full line on track for completion by June.

Commercial Times notes that the rise of CoPoS underscores an industry shift toward panelization as a key solution to advanced packaging bottlenecks: as AI chip reticle sizes continue to expand-such as NVIDIA's Rubin GPU reaching 5.5x-a standard 12-inch wafer can now accommodate just seven, or in some cases as few as four, units. Square panel formats, as per the report, offer a step-change in utili...