India, Sept. 18 -- There was a fireside chat on: From concept to silicon: Strengthening India's design enablement and test ecosystem, at the ongoing Semicon India 2026.

The participants were Amit Khanuja, R&D Engineering, IP Group, Synopsys, and Hitesh Garg, VP & India Country Manager, and Design Enablement Leader, NXP. Dr. Sudarshan, Executive Director, CDAC, Bangalore, was the moderator.

Dr. Sudarshan said the first barrier is access to technology. Second one is the cost of such tools for semiconductors. Infrastructure is not easy to build. Third, how can you estimate and validate your design. Fourth, timeline dimension. Given such barriers, Semicon 1.0 has removed them, thanks to all of the players. Design and testing is integrated....