India, Aug. 27 -- Achronix Semiconductor Corporation has announced the availability of its JESD204C Internet Protocol (IP) core for the Speedster7t FPGA family, providing a high-speed interface between advanced analogue-to-digital converters (ADCs), digital-to-analogue converters (DACs) and programmable logic.

Each core supports data rates of up to 32 Gbps per lane and up to eight lanes per link, providing an aggregate serial line rate of up to 256 Gbps. Up to four cores can be combined to provide aggregate throughput of up to 1 Tbps.

The standards-based IP core supports high-speed JESD204B and JESD204C converters from suppliers including Analog Devices and Texas Instruments, allowing Speedster7t FPGAs to be integrated into converter-ba...