US Patent Issued to Volantis Semiconductor on Aug. 25 for "Wafer-scale integration with a stiffening isometric grid array" (California Inventors)

ALEXANDRIA, Va., Aug. 25 -- United States Patent no. 12,721,244, issued on Aug. 25, was assigned to Volantis Semiconductor Inc. (Portland, Ore.).

"Wafer-scale integration with a stiffening isometric grid array" was invented by Kevin Nan Lam (Pleasanton, Calif.) and Tapabrata Ghosh (Oakland, Calif.).

According to the abstract* released by the U.S. Patent & Trademark Office: "Techniques for stiffening are disclosed. A wafer-scale silicon interposer (WSSI) is accessed. A front side of the WSSI is bonded to a plurality of functional chips. The WSSI includes a plurality of through-silicon vias (TSVs). The WSSI is stiffened. The stiffening is based on an isometric grid array (IGA). The stiffening includes inserting, into the IGA, a back side of...