US Patent Issued to Tokyo Electron on Feb. 17 for "Highly regular logic design for efficient 3D integration" (New York Inventors)

ALEXANDRIA, Va., Feb. 17 -- United States Patent no. 12,557,392, issued on Feb. 17, was assigned to Tokyo Electron Ltd. (Tokyo).

"Highly regular logic design for efficient 3D integration" was invented by Lars Liebmann (Mechanicville, N.Y.), Jeffrey Smith (Clifton Park, N.Y.), Daniel Chanemougame (Nishayuna, N.Y.) and Anton deVilliers (Clifton Park, N.Y.).

According to the abstract* released by the U.S. Patent & Trademark Office: "An integrated circuit includes an array of unit cells, each unit cell of which including field effect transistors arranged in a stack. Local interconnect structures form select conductive paths between select terminals of the field effect transistors to define cell circuitry that is confined within each unit cell...