US Patent Issued to Taiwan Semiconductor Manufacturing on June 2 for "Multiple gate patterning methods towards future nanosheet scaling" (Taiwanese Inventors)

ALEXANDRIA, Va., June 2 -- United States Patent no. 12,648,181, issued on June 2, was assigned to Taiwan Semiconductor Manufacturing Co. Ltd. (Hsinchu, Taiwan).

"Multiple gate patterning methods towards future nanosheet scaling" was invented by Lung-Kun Chu (Hsinchu, Taiwan), Jia-Ni Yu (Hsinchu, Taiwan), Chun-Fu Lu (Hsinchu, Taiwan), Mao-Lin Huang (Hsinchu, Taiwan), Kuo-Cheng Chiang (Hsinchu, Taiwan) and Chih-Hao Wang (Hsinchu, Taiwan).

According to the abstract* released by the U.S. Patent & Trademark Office: "A method for forming a semiconductor device is provided. The method includes forming a plurality of first channel nanostructures and a plurality of second channel nanostructures in an n-type device region and a p-type device region...