US Patent Issued to Synopsys on Oct. 27 for "Automated design hierarchy identification and simplified reduced model generation for static verification of circuit designs" (Indian Inventors)

ALEXANDRIA, Va., Oct. 27 -- United States Patent no. 12,775,764, issued on Oct. 27, was assigned to Synopsys Inc. (Sunnyvale, Calif.).

"Automated design hierarchy identification and simplified reduced model generation for static verification of circuit designs" was invented by Gaurav Pratap (Noida, India), Bhaskar Pal (Bangalore, India) and Mohit Kumar (New Delhi).

According to the abstract* released by the U.S. Patent & Trademark Office: "A system performs efficient verification of a circuit design. The system receives a circuit design including circuit blocks. The system identifies some of the circuit blocks as modeled circuit blocks. The system generates simplified reduced models (SRMs) for the modeled circuit blocks. A simplified redu...