US Patent Issued to Synopsys on June 23 for "Performance and throughput when modeling half cycle paths during emulation or prototyping" (American, Singaporean, French Inventors)

ALEXANDRIA, Va., July 15 -- United States Patent no. 12,664,341, issued on June 23, was assigned to Synopsys Inc. (Sunnyvale, Calif.).

"Performance and throughput when modeling half cycle paths during emulation or prototyping" was invented by Alexander Rabinovitch (Shrewsbury, Mass.), Cedric Jean Alquier (Wissous, France), Prashant Saxena (Portland, Ore.) and Sivaprasad Acharaya (Singapore).

According to the abstract* released by the U.S. Patent & Trademark Office: "A method of verifying a logic circuit design by a hardware emulation system, includes, in part, receiving a netlist of the logic circuit design configured to operate in response to positive edges of a first clock signal, and transforming each of a first multitude of flip-flops...