US Patent Issued to Synopsys on Aug. 25 for "Delay calculation with pattern matching for static timing analysis" (California Inventors)

ALEXANDRIA, Va., Aug. 25 -- United States Patent no. 12,717,991, issued on Aug. 25, was assigned to Synopsys Inc. (Sunnyvale, Calif.).

"Delay calculation with pattern matching for static timing analysis" was invented by Peivand Tehrani (Campbell, Calif.), Chenwei Dustin Liu (Milpitas, Calif.) and Ahmed Shebaita (Fremont, Calif.).

According to the abstract* released by the U.S. Patent & Trademark Office: "A method of performing static timing analysis for a circuit design includes, in part, identifying a multitude of logic blocks of the circuit design matching a design pattern; determining values of a multitude of electrical properties associated with a first logic block representative of each of the plurality of logic blocks; and determini...