US Patent Issued to Silicon Storage Technology on Oct. 6 for "Address fault detection in a memory system" (California Inventor)

ALEXANDRIA, Va., Oct. 6 -- United States Patent no. 12,755,788, issued on Oct. 6, was assigned to Silicon Storage Technology Inc. (San Jose, Calif.).

"Address fault detection in a memory system" was invented by Hieu Van Tran (San Jose, Calif.).

According to the abstract* released by the U.S. Patent & Trademark Office: "Various examples of memory systems comprising an address fault detection system are disclosed. The memory system comprises a first memory array, a row decoder, and an address fault detection system comprising a second array, wherein the row decoder decodes row addresses into word lines, each word line coupled to a row of cells in the first array and a row of cells in the second array. The second array contains digital bits ...