US Patent Issued to Raytheon on July 14 for "Low-stress dielectric layer, planarization method, and low-temperature processing for 3D-integrated electrical device" (California Inventors)

ALEXANDRIA, Va., July 14 -- United States Patent no. 12,684,896, issued on July 14, was assigned to Raytheon Co. (Arlington, Va.).

"Low-stress dielectric layer, planarization method, and low-temperature processing for 3D-integrated electrical device" was invented by Chad Fulk (Goleta, Calif.), Sean P. Kilcoyne (Lompoc, Calif.), Stuart Farrell (Goleta, Calif.), Eric Miller (Lompoc, Calif.) and Andrew Clarke (Goleta, Calif.).

According to the abstract* released by the U.S. Patent & Trademark Office: "An electrical device includes a substrate, a dielectric layer supported by the substrate, and an electrically conductive vertical interconnect extending through the dielectric layer. The dielectric layer may be formed at low-temperature below t...