US Patent Issued to RAMBUS on Feb. 17 for "Clocking architecture supporting multiple data rates and reference edge selection" (California Inventors)

ALEXANDRIA, Va., Feb. 17 -- United States Patent no. 12,555,621, issued on Feb. 17, was assigned to RAMBUS INC. (San Jose, Calif.).

"Clocking architecture supporting multiple data rates and reference edge selection" was invented by Panduka Wijetunga (Thousand Oaks, Calif.) and Abhishek Desai (Newbury Park, Calif.).

According to the abstract* released by the U.S. Patent & Trademark Office: "A clocking architecture for a memory module is configurable to independently select either rising or falling edges of an input clock as respective references for generation of an internal clock and an output clock. The clocking architecture supports reference edge selection in both a single data rate (SDR) mode and a double data rate (DDR) mode while ma...