US Patent Issued to QuickLogic on June 2 for "Sectional configuration for programmable logic devices" (California Inventors)

ALEXANDRIA, Va., June 2 -- United States Patent no. 12,647,118, issued on June 2, was assigned to QuickLogic Corp. (San Jose, Calif.).

"Sectional configuration for programmable logic devices" was invented by Ket Chong Yap (San Jose, Calif.) and Chihhung Liao (Fremont, Calif.).

According to the abstract* released by the U.S. Patent & Trademark Office: "A bit line (BL) may be coupled at a first end to a BL driver (BLD) and at a second end to a BL receiver (BLR). The BL include a plurality of sections and each BL section may be coupled to at least one corresponding sectional configuration memory latch controlled by: at least one sectional word line write (WLW-k) signal, which when asserted enables data to be written into the at least one cor...