US Patent Issued to NVIDIA on May 5 for "Retention mode low leakage high performance bit line clamping scheme based on an output latch state" (California, Pennsylvania Inventors)

ALEXANDRIA, Va., May 5 -- United States Patent no. 12,620,438, issued on May 5, was assigned to NVIDIA Corp. (Santa Clara, Calif.).

"Retention mode low leakage high performance bit line clamping scheme based on an output latch state" was invented by Lalit Gupta (Fremont, Calif.) and Cagri Erbagci (Pittsburgh).

According to the abstract* released by the U.S. Patent & Trademark Office: "An on-chip static RAM (SRAM) is disclosed. In one embodiment, the on-chip SRAM includes an array of memory cells arranged in columns and rows, a read bit line for each column of the array of memory cells, and an output latch to store a bit for one of the array of memory cells when the on-chip SRAM is in a retention mode. In one embodiment, each memory cell i...