US Patent Issued to Micron Technology on Oct. 27 for "Memory pillar selection transistor evaluation" (Idaho Inventors)

ALEXANDRIA, Va., Oct. 27 -- United States Patent no. 12,776,370, issued on Oct. 27, was assigned to Micron Technology Inc. (Boise, Idaho).

"Memory pillar selection transistor evaluation" was invented by Avinash Rajagiri (Boise, Idaho) and Pitamber Shukla (Boise, Idaho).

According to the abstract* released by the U.S. Patent & Trademark Office: "Methods, systems, and devices for memory pillar selection transistor evaluation are described. A memory system may be configured to monitor threshold voltage characteristics of pillar selection transistors, which may include evaluations relative to certain subsets of the pillar selection transistors. For example, an activation voltage may be applied to the pillar selection transistors to determine ...