US Patent Issued to Micron Technology on July 7 for "Alternative erase schemes for reliability-risk word lines" (California Inventors)

ALEXANDRIA, Va., July 7 -- United States Patent no. 12,676,198, issued on July 7, was assigned to Micron Technology Inc. (Boise, Idaho).

"Alternative erase schemes for reliability-risk word lines" was invented by Yu-Chung Lien (San Jose, Calif.) and Zhenming Zhou (San Jose, Calif.).

According to the abstract* released by the U.S. Patent & Trademark Office: "In some implementations, a memory device may receive, from a host device, an erase command associated with erasing host data from a portion of a memory. The memory device may determine that the portion of the memory is associated with a reliability risk. The memory device may perform, based on determining that the portion of the memory is associated with the reliability risk, an altern...