ALEXANDRIA, Va., Feb. 24 -- United States Patent no. 12,563,810, issued on Feb. 24, was assigned to Intel Corp. (Santa Clara, Calif.).
"Selective backside recessing of source and drain regions" was invented by Jaladhi Mehta (Beaverton, Ore.), Giorgio Mariottini (Hillsboro, Ore.), Weihong Gao (Portland, Ore.), Lin Hu (Portland, Ore.), Conor P. Puls (Portland, Ore.), Brian Greene (Portland, Ore.) and Chung-Hsun Lin (Portland, Ore.).
According to the abstract* released by the U.S. Patent & Trademark Office: "Techniques are provided herein to form an integrated circuit having source and/or drain regions with shaped bottom surfaces to reduce parasitic capacitance. In an example, the bottom portions of the source and/or drain regions may be etc...