US Patent Issued to Intel on Aug. 25 for "Hierarchical thread scheduling based on multi-parameter signal barriers" (California, Oregon Inventors)

ALEXANDRIA, Va., Aug. 25 -- United States Patent no. 12,717,582, issued on Aug. 25, was assigned to Intel Corp. (Santa Clara, Calif.).

"Hierarchical thread scheduling based on multi-parameter signal barriers" was invented by Hong Jiang (El Dorado Hills, Calif.), Sabareesh Ganapathy (Santa Clara, Calif.), Xinmin Tian (Fremont, Calif.), Fangwen Fu (Folsom, Calif.) and James Valerio (North Plains, Ore.).

According to the abstract* released by the U.S. Patent & Trademark Office: "Examples described herein relate to a graphics processing apparatus that includes a memory device and a graphics processing unit (GPU) coupled to the memory device. The GPU can be configured to: execute an instruction thread; determine if a signal barrier is associat...