US Patent Issued to Intel on April 21 for "Constructing hierarchical clock gating architectures via rewriting" (British, American Inventors)

ALEXANDRIA, Va., April 21 -- United States Patent no. 12,608,070, issued on April 21, was assigned to Intel Corp. (Santa Clara, Calif.).

"Constructing hierarchical clock gating architectures via rewriting" was invented by Samuel Coward (London), Theo Drane (El Dorado Hills, Calif.), George A. Constantinides (Santa Clara, Calif.) and Emiliano Morini (El Dorado Hills, Calif.).

According to the abstract* released by the U.S. Patent & Trademark Office: "Described herein is a technique to enable the construction of hierarchical clock gating architectures via e-graph rewriting. Automated clock gating relies on multiplexor (mux) tree analysis and constructs simple register enable signals. A framework is provided to detect non-mux based opportuni...