US Patent Issued to Intel on April 14 for "Method and apparatus to perform training on a data bus between a dynamic random access memory (DRAM) and a data buffer on a buffered dual in-line memory module" (Oregon, North Carolina, Texas Inventors)

ALEXANDRIA, Va., April 15 -- United States Patent no. 12,603,115, issued on April 14, was assigned to Intel Corp. (Santa Clara, Calif.).

"Method and apparatus to perform training on a data bus between a dynamic random access memory (DRAM) and a data buffer on a buffered dual in-line memory module" was invented by Saravanan Sethuraman (Portland, Ore.), Tonia M. Rose (Wendell, N.C.), George Vergis (Portland, Ore.) and John V. Lovelace (Driftwood, Texas).

According to the abstract* released by the U.S. Patent & Trademark Office: "System boot time is decreased by performing Memory Receive enable (MRE) training and MDQ-MDQS Read Delay (MRD) training on a buffered Dual In-Line Memory Module (DIMM). MRE training configures the time at which a da...