US Patent Issued to Intel on April 14 for "Gate end cap and boundary placement in transistor structures for N-metal oxide semiconductor (N-MOS) performance tuning" (Oregon Inventors)

ALEXANDRIA, Va., April 15 -- United States Patent no. 12,604,494, issued on April 14, was assigned to Intel Corp. (Santa Clara, Calif.).

"Gate end cap and boundary placement in transistor structures for N-metal oxide semiconductor (N-MOS) performance tuning" was invented by Andrew Smith (Hillsboro, Ore.), Brian Greene (Portland, Ore.), Seonghyun Paik (Hillsboro, Ore.), Omair Saadat (Portland, Ore.), Chung-Hsun Lin (Portland, Ore.) and Tahir Ghani (Portland, Ore.).

According to the abstract* released by the U.S. Patent & Trademark Office: "A transistor structure includes a channel region including first sidewall. A gate electrode includes a first layer having a first portion adjacent to the first sidewall and a second portion adjacent to a...