ALEXANDRIA, Va., Feb. 24 -- United States Patent no. 12,563,725, issued on Feb. 24, was assigned to Intel NDTM US LLC (Santa Clara, Calif.).
"Parallel staircase 3D NAND" was invented by Deepak Thimmegowda (Fremont, Calif.), Chang Wan Ha (San Ramon, Calif.), Md Rezaul Karim Nishat (Santa Clara, Calif.), Liu Liu (Dalian, China), Yuanrong Shui (Dalian, China), Kwame Eason (East Palo Alto, Calif.), Ahmed Reza (San Jose, Calif.) and Hoon Koh (San Jose, Calif.).
According to the abstract* released by the U.S. Patent & Trademark Office: "Systems, apparatuses, and methods may provide for technology that arranges stair wells for memory devices. The memory device includes a memory array and a memory block coupled to the memory array. The memory blo...