US Patent Issued to Cadence Design Systems on Sept. 8 for "Non-critical child node-based insertion delay optimization in circuit design" (American, Brazilian Inventors)

ALEXANDRIA, Va., Sept. 8 -- United States Patent no. 12,730,958, issued on Sept. 8, was assigned to Cadence Design Systems Inc. (San Jose, Calif.).

"Non-critical child node-based insertion delay optimization in circuit design" was invented by Necati Uysal (Austin, Texas), Sheiny Fabre Almeida (Sao Jose, Brazil), Natarajan Viswanathan (Austin, Texas), Charles Jay Alpert (Cedar Park, Texas) and Amin Farshidi (Austin, Texas).

According to the abstract* released by the U.S. Patent & Trademark Office: "Various embodiments provide for optimizing (e.g., reducing) insertion delay in a circuit design based on one or more non-critical child nodes of a critical node of a routing tree, which can be performed by an electronic design automation (EDA) s...