US Patent Issued to Cadence Design Systems on June 30 for "Programmable sequence-driven hardware trigger for multiple FPGA system" (American, Indian Inventors)

ALEXANDRIA, Va., July 16 -- United States Patent no. 12,670,307, issued on June 30, was assigned to Cadence Design Systems Inc. (San Jose, Calif.).

"Programmable sequence-driven hardware trigger for multiple FPGA system" was invented by Shantanu Telharkar (San Jose, Calif.), Sheng-Shiung Wu (Pleasanton, Calif.), Raju Joshi (Los Altos, Calif.), Vasant Ramabadran (San Jose, Calif.), Suresh Gopalrathnam (Los Altos, Calif.) and Anand Gupta (Ghaziabad, India).

According to the abstract* released by the U.S. Patent & Trademark Office: "Disclosed herein are systems and methods of a prototyping system for circuit design testing. The prototyping system employs hardware ("Debug FPGA") that performs a series of Boolean evaluations according to testb...