US Patent Issued to Cadence Design Systems on April 21 for "Phase locked loop architecture with reduced bandwidth variation" (California, Maryland Inventors)

ALEXANDRIA, Va., April 21 -- United States Patent no. 12,609,706, issued on April 21, was assigned to Cadence Design Systems Inc. (San Jose, Calif.).

"Phase locked loop architecture with reduced bandwidth variation" was invented by Shaojun Ma (San Jose, Calif.), Didem Zeliha Turker Melek (San Jose, Calif.) and Stephen Thomas Williams (Woodbine, Md.).

According to the abstract* released by the U.S. Patent & Trademark Office: "Embodiments included herein are directed towards a phase-locked loop (PLL) circuit. Embodiments may include a phase frequency detector circuit configured to receive an input signal. Embodiments may further include a charge pump circuit configured to receive an output signal from the phase frequency detector circuit. T...