US Patent Issued to Cadence Design Systems on April 14 for "Subranging digital to time converter-based fractional phase locked loop architecture" (Canadian, Indian, American Inventors)

ALEXANDRIA, Va., April 15 -- United States Patent no. 12,603,655, issued on April 14, was assigned to Cadence Design Systems Inc. (San Jose, Calif.).

"Subranging digital to time converter-based fractional phase locked loop architecture" was invented by Sudipta Sarkar (San Jose, Calif.), Angus McLaren (Dundas, Canada), Meenakshi S. (Bengaluru, India), Priya T K (Bangalore, India), Srivatsa Ranganatha (Bangalore, India), Mohammed Ranjbar (San Jose, Calif.), Paul Lee (San Francisco), Shwetabh Verma (Los Altos, Calif.) and George Chung Fai Ng (Markham, Canada).

According to the abstract* released by the U.S. Patent & Trademark Office: "Embodiments included herein are directed towards a subranging digital to time converter-based fractional pha...