ALEXANDRIA, Va., March 24 -- United States Patent no. 12,585,850, issued on March 24, was assigned to Astera Labs Inc. (San Jose, Calif.).
"Cascaded-scenario logic analyzer" was invented by Hemant Vinchure (San Jose, Calif.), Anh T. Tran (Elk Grove, Calif.) and Ken (Keqin) Han (Fremont, Calif.).
According to the abstract* released by the U.S. Patent & Trademark Office: "A chip-embedded logic analyzer autonomously sequences between logic analysis scenarios, dynamically revising match criteria and match-responsive behavior as match conditions for each successive scenario are met. Through this cascading-scenario operation, the logic analyzer may log selected debug vectors as and/or after complex sequences of device conditions unfold, enablin...