US Patent Issued to Applied Materials on Sept. 1 for "Source drain formation in gate all around transistor" (California Inventors)

ALEXANDRIA, Va., Sept. 1 -- United States Patent no. 12,727,214, issued on Sept. 1, was assigned to Applied Materials Inc. (Santa Clara, Calif.).

"Source drain formation in gate all around transistor" was invented by Ashish Pal (San Ramon, Calif.), El Mehdi Bazizi (San Jose, Calif.) and Benjamin Colombeau (San Jose, Calif.).

According to the abstract* released by the U.S. Patent & Trademark Office: "Semiconductor devices and methods of manufacturing the same are described. The method includes forming a bottom dielectric isolation (BDI) layer on a substrate and depositing a template material in the source/drain trench. The template material is etched and then crystallized. Epitaxially growth of the source and drain regions then proceeds, w...