US Patent Issued to Akeana on June 23 for "Coherent hierarchical cache line tracking" (California Inventor)

ALEXANDRIA, Va., July 15 -- United States Patent no. 12,664,096, issued on June 23, was assigned to Akeana Inc. (Santa Clara, Calif.).

"Coherent hierarchical cache line tracking" was invented by Sanjay Patel (San Ramon, Calif.).

According to the abstract* released by the U.S. Patent & Trademark Office: "Techniques for coherency management based on coherent hierarchical cache line tracking are disclosed. A plurality of processor cores is accessed. Each processor of the plurality of processor cores includes a local cache. A hierarchical cache is coupled to the plurality of processor cores. The hierarchical cache is shared among the plurality of processor cores. Coherency between the plurality of processor cores and the hierarchical cache is...