US Patent Issued to Adeia Semiconductor Technologies on July 21 for "System and method for providing 3D wafer assembly with known-good-dies" (California Inventors)

ALEXANDRIA, Va., July 21 -- United States Patent no. RE50,965, issued on July 21, was assigned to Adeia Semiconductor Technologies LLC (San Jose, Calif.).

"System and method for providing 3D wafer assembly with known-good-dies" was invented by Hong Shen (Palo Alto, Calif.), Liang Wang (Newark, Calif.) and Guilian Gao (San Jose, Calif.).

According to the abstract* released by the U.S. Patent & Trademark Office: "Systems and methods for providing 3D wafer assembly with known-good-dies are provided. An example method compiles an index of dies on a semiconductor wafer and removes the defective dies to provide a wafer with dies that are all operational. Defective dies on multiple wafers may be removed in parallel, and resulting wafers with all...