INTERNATIONAL PATENT: MICROCHIP TECHNOLOGY INCORPORATED FILES APPLICATION FOR "I3C ERROR STATES TEST STRATEGY"

GENEVA, May 12 -- MICROCHIP TECHNOLOGY INCORPORATED (2355 West Chandler BoulevardChandler, AZ 85224) filed a patent application (PCT/US2025/018434) for "I3C ERROR STATES TEST STRATEGY" on Mar 05, 2025. With publication no. WO/2026/095976, the details related to the patent application was published on May 07, 2026.

Notably, the patent application was submitted under the International Patent Classification (IPC) system, which is managed by the World Intellectual Property Organization (WIPO).

Inventor(s): VISWANATHAN, Vivek (FF1, Pearl Ixora, Plot No 45, 2nd StreetMunusamy Nagar, MedavakkamChennai, Tamil Nadu 600100)

Abstract: An integrated circuit (IC) for testing an I3C device is provided. The IC may include a start/stop detection logic b...