INTERNATIONAL PATENT: ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC. FILES APPLICATION FOR "MICROLED VERTICAL REDUNDANCY TO COVER FOR DEFECTIVE PIXELS IN DISPLAYS AND METHODS RELATED THERETO"

GENEVA, May 12 -- ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC. (3025 Orchard ParkwaySan Jose, California 95134) filed a patent application (PCT/US2025/053390) for "MICROLED VERTICAL REDUNDANCY TO COVER FOR DEFECTIVE PIXELS IN DISPLAYS AND METHODS RELATED THERETO" on Oct 30, 2025. With publication no. WO/2026/096801, the details related to the patent application was published on May 07, 2026.

Notably, the patent application was submitted under the International Patent Classification (IPC) system, which is managed by the World Intellectual Property Organization (WIPO).

Inventor(s): ZHAO, Oliver (3025 Orchard ParkwaySan Jose, California 95134), KATKAR, Rajesh (3025 Orchard ParkwaySan Jose, California 95134)

Abstract: A display device compr...