Intellectual Property India Publishes Patent Application for System And Method For Implementing Smart Clock Gating In An Arithmetic Logic Unit (alu)

MUMBAI, India, Aug. 12 -- Intellectual Property India has published a patent application (202641094154 A) filed by Presidency University on August 04, 2026, for System And Method For Implementing Smart Clock Gating In An Arithmetic Logic Unit (alu).

Inventor includes Aruna M.

The application for the patent was published on August 07, 2026, under issue no. 32/2026.

Abstract: ABSTRACT System and Method for Implementing Smart Clock Gating in an Arithmetic Logic Unit (ALU) The present invention relates to a system and method for implementing intelligent clock gating in an arithmetic logic unit (ALU) for reducing dynamic power consumption in digital systems. The system comprises an input module (101) configured to receive input operands, an o...