MUMBAI, India, June 30 -- Intellectual Property India has published a patent application (202641073914 A) filed by Mohan Babu University on June 15, 2026, for System And Method For High-Speed Multiplier Design Using Stacker-Based Binary Compressors And Vedic Multiplication Algorithm.
Inventors include Mr M. Ventaka Naresh; and Mr. G. Naresh.
The application for the patent was published on June 26, 2026, under issue no. 26/2026.
Abstract: The present invention relates to a multiplier architecture designed for high-speed digital arithmetic operations. Multipliers are widely used in applications such as digital signal processing, machine learning, image processing, and embedded computing systems. The proposed design integrates the Urdhva Ti...