MUMBAI, India, Nov. 2 -- Intellectual Property India has published a patent application (202641107247 A) filed by Yashasvi Alladi on September 07, 2026, for System And Method For Cold-Start Latency Mitigation In Scale-To-Zero Gpu Inference Endpoints By Repurposing A Session-Security Timeout As A Coordinated Timing Input.

Inventor includes Yashasvi Alladi.

The application for the patent was published on October 30, 2026, under issue no. 44/2026.

Abstract: Embodiments of the present disclosure relate to a computer-implemented system and method for cold-start latency mitigation in scale-to-zero inference endpoints. A Coordinated Timing Module (122) computes a keep-alive throttle interval from the same Session Idle Timeout Parameter (110) th...