Intellectual Property India Publishes Patent Application for Sparsity-Aware Mixed-Precision Reconfigurable Systolic Array For Neural Network Acceleration

MUMBAI, India, Oct. 5 -- Intellectual Property India has published a patent application (202641113884 A) filed by Saveetha Engineering College on September 23, 2026, for Sparsity-Aware Mixed-Precision Reconfigurable Systolic Array For Neural Network Acceleration.

Inventor includes Sunitha T.

The application for the patent was published on October 02, 2026, under issue no. 40/2026.

Abstract: The invention relates to an architecture and method for a systolic array that operates at runtime to strengthen computing of a deep neural network on a VLSI-based Al hardware accelerator. Systolic arrays based on the principle that they skip individual multiply-accumulate opefations tend to be unable to match the throughput or energy efficiency of the...