Intellectual Property India Publishes Patent Application for Small Loop Delay Clock And Data Recovery Block For High-Speed Next Generation C-Phy

MUMBAI, India, July 13 -- Intellectual Property India has published a patent application (202548125213 A) filed by Qualcomm Incorporated on December 11, 2025, for Small Loop Delay Clock And Data Recovery Block For High-Speed Next Generation C-Phy.

Inventors include Duan, Ying; Wu, Jing; and Chou, Shih-Wei.

The application for the patent was published on July 10, 2026, under issue no. 28/2026.

Abstract: ABSTRACT SMALL LOOP DELAY CLOCK AND DATA RECOVERY BLOCK FOR HIGH-SPEED NEXT GENERATION C- PHY A clock recovery apparatus comprising: a pulse merger circuit having a plurality of inputs, a plurality of delay circuits, each of the plurality of delay circuits associated with a respective one of the plurality of inputs, a plurality of logic ga...