Intellectual Property India Publishes Patent Application for Reduced Gate Edge Capacitance

MUMBAI, India, July 13 -- Intellectual Property India has published a patent application (202617071477 A) filed by International Business Machines on June 09, 2026, for Reduced Gate Edge Capacitance.

Inventors include Ando, Takashi; Vega, Reinaldo Number; Lanzillo, Nicholas, Anthony; Wolpert, David; and Mazza, James, Patrick.

The application for the patent was published on July 10, 2026, under issue no. 28/2026.

Abstract: A field effect transistor (FET) device is provided. The FET device includes an active region and a gate. The active region includes a source at a first end of the active region and a drain at a second end of the active region. The gate extends across the active region and includes at least one end extending past a corre...