Intellectual Property India Publishes Patent Application for Modifying The Parallel Prefix Adder By Implementing A Low Power Hybrid Full Adder

MUMBAI, India, July 13 -- Intellectual Property India has published a patent application (202541000645 A) filed by Hindusthan Institute Of Technology on January 03, 2025, for Modifying The Parallel Prefix Adder By Implementing A Low Power Hybrid Full Adder.

Inventors include Dr. C. Natarajan; Mr. A. Abdul Hayum; Dr. B. Paulchamy; Ms. N. Rambrabha; Mr. A. Vidhyaseka R; Mrs. L. Yogapriya; and Dr. J. Ramya.

The application for the patent was published on July 10, 2026, under issue no. 28/2026.

Abstract: 7. ABSTRACT OF THE INVENTION: Parallel Prefix Adders (PPAs) are crucial in high-performance computing and digital signal processing due to their efficiency in performing fast arithmetic operations. This paper focuses on enhancing the PPA's p...