Intellectual Property India Publishes Patent Application for Method And System For Digital Twin Assisted Compile-Time Optimization Of A Heterogeneous Fpga System

MUMBAI, India, July 13 -- Intellectual Property India has published a patent application (202641082078 A) filed by Indian Institute Of Technology Hyderabad on July 03, 2026, for Method And System For Digital Twin Assisted Compile-Time Optimization Of A Heterogeneous Fpga System.

Inventors include Ratnala Vinay; Parveen Nisha; Vivek Muthke; and Amit Acharyya.

The application for the patent was published on July 10, 2026, under issue no. 28/2026.

Abstract: The present invention discloses a method (600) and system (100) for compile-time optimization of a heterogeneous FPGA system. A target workload is received for deployment on the heterogeneous FPGA system, and a digital twin module (104) corresponding to the heterogeneous FPGA system gene...