Intellectual Property India Publishes Patent Application for Low Power Fpga Based Alu Design Using Clock Gating Technique

MUMBAI, India, Sept. 28 -- Intellectual Property India has published a patent application (202641111377 A) filed by Srm Institute Of Science And Technology Tiruchirappalli on September 17, 2026, for Low Power Fpga Based Alu Design Using Clock Gating Technique.

Inventors include Harshith Teella; Kodali Harshit Sai; and Dr. V. Manikandan.

The application for the patent was published on September 25, 2026, under issue no. 39/2026.

Abstract: The invention at hand reveals a low power Arithmetic Logic Unit (ALU) designed on a Field Programmable Gate Array (FPGA) by one of a clock gating algorithm in order to reduce dynamic power spending. Most of the traditional FPGA-based designs operate by constantly switching the clock signal whether they a...