Intellectual Property India Publishes Patent Application for Gnrfet Based Ternary Half Adder And Multiplier

MUMBAI, India, Sept. 28 -- Intellectual Property India has published a patent application (202641112689 A) filed by G. Pullaiah College Of Engineering And Technology on September 20, 2026, for Gnrfet Based Ternary Half Adder And Multiplier.

Inventors include T. Kishore; Dr. P. Venkatramana; Dr. V. Vijaya Kishore; M. Kiranmayee; Dr. Pasuluri Bindu Swetha; T. Deepa; R. Deepthi Crestose Rebekah; P. Raga Chandrika; A. Sreepradha; and Dr. S. Javid Basha.

The application for the patent was published on September 25, 2026, under issue no. 39/2026.

Abstract: The detailed design of ternary logic schematics is proposed in this study. The ternary logics offer fast computations, reduced chip size and reduced interconnect complexity compared to conve...