Intellectual Property India Publishes Patent Application for Generating A Tiled Register Transfer Level Design

MUMBAI, India, Sept. 28 -- Intellectual Property India has published a patent application (202511012390 A) filed by Baya Systems, Inc. on February 13, 2025, for Generating A Tiled Register Transfer Level Design.

Inventors include Aditya Gurjar; Eric Norige; and Narayana Sri Harsha Gade.

The application for the patent was published on September 25, 2026, under issue no. 39/2026.

Abstract: A method for generating a tiled Register Transfer Level (RTL) design includes determining a number of identification bits required to uniquely identify each instance within the tiled RTL design, utilizing local bits for local identification, context bits for contextual distinction, and parent bits for hierarchical association. Further, the method include...