Intellectual Property India Publishes Patent Application for Design And Validation Of Mixed Logic 2-To-4 Decoders Using 32 Nm Finfet Technology

MUMBAI, India, July 7 -- Intellectual Property India has published a patent application (202641079270 A) filed by Mohan Babu University on June 27, 2026, for Design And Validation Of Mixed Logic 2-To-4 Decoders Using 32 Nm Finfet Technology.

Inventors include Ms. Kakarla Praveena; Mr. Penujuri Ramaprabhas; Mr. Shaik Mahaboob Basha; Mr. Korrapati Venkata Sai Chowdary; and Mr. Aka Dhanesh.

The application for the patent was published on July 03, 2026, under issue no. 27/2026.

Abstract: This paper introduces the design and implementation of a 2x4 decoder using FinFET technology at the 32nm process node, leveraging transmission gate logic and dual-value logic to optimize performance. LP (Low power) and LPI(Low power inversion), HP(High Power...