Intellectual Property India Publishes Patent Application for Asic Implementation Of An Adptive Precision 32-Bit Arithmetic Logic Unit Using Cadence Digital Design Flow

MUMBAI, India, Aug. 12 -- Intellectual Property India has published a patent application (202641084683 A) filed by Sivesh Kumar S; R Madhumttha; and Latha P on July 10, 2026, for Asic Implementation Of An Adptive Precision 32-Bit Arithmetic Logic Unit Using Cadence Digital Design Flow.

Inventors include Sivesh Kumar S; R Madhumttha; and Latha P.

The application for the patent was published on August 07, 2026, under issue no. 32/2026.

Abstract: The invention relates to the design and performance evaluation of an Adaptive Precision 32-bit Arithmetic Logic Unit implemented using Verilog HDL and Cadence Digital Design Flow. Unlike conventional fixed-precision ALUs that activate the entire 32-bit datapath for every operation, the proposed arc...