Intellectual Property India Publishes Patent Application for An Efficient High-Precision Redundancy Multiplier Employing A Fast Bipartitioned Hybrid Adder

MUMBAI, India, July 7 -- Intellectual Property India has published a patent application (202641075337 A) filed by Hindusthan Institute Of Technology on June 18, 2026, for An Efficient High-Precision Redundancy Multiplier Employing A Fast Bipartitioned Hybrid Adder.

Inventors include Dr. C. Natarajan; Dr. K. Mahendrakan; Dr. B. Paulchamy; V. Muruganandam; Dr. A. Purushothaman; A. Abdul Hayum; A. Vidhyasekar; R. Karuppusamy; B. Hakkem; and R. Ganeshkishore.

The application for the patent was published on July 03, 2026, under issue no. 27/2026.

Abstract: Ensuring the seamless operation of modem digital systems requires a delicate balance between computational performance, fault tolerance, and resource efficiency. Conventional methods for ac...